Showing 21-38 of 38 projects
RISC-V Assembly Programmer's Manual, a reference for developers working with RISC-V architecture.
RARS is a RISC-V assembler and runtime simulator for educational and development purposes.
An open-source RISC-V supervisor binary interface, not focused on AI coding tools.
A self-hosting and educational C optimizing compiler, useful for building low-level system programming tools.
A random instruction generator for RISC-V processor verification, written in Python.
A Rust library that provides a RISC-V Supervisor Binary Interface (SBI) for embedded Rust development.
Genode OS Framework is a microkernel-based operating system focused on security, modularity, and portability.
RVVM is a RISC-V emulator written in C, allowing developers to run RISC-V applications on their systems.
A RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform, written in SystemVerilog.
A 32-bit superscalar RISC-V CPU implementation written in Verilog for FPGA and ASIC applications.
RISC-V tools including an ISA simulator and test suite for RISC-V processors.
This repository contains a set of RISC-V tests used for verifying RISC-V processor implementations.
This is a course on building a RISC-V operating system from scratch, not a vibe coder tool.
A working draft of the proposed RISC-V V vector extension for low-power embedded systems.
A low-level library for accessing RISC-V processors in Rust, suitable for embedded systems development.
RISC-V XV6/Linux SoC, a low-power, open-source CPU design for developers working on hardware and embedded systems.
FPGA-based RISC-V SoC running Debian Linux, useful for embedded systems and hardware-accelerated computing
A fast, lightweight, and dependency-free RISC-V emulator and sandbox for developers working on RISC-V projects.
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