Showing 101-120 of 126 projects
Open-source GPU in Verilog, loosely based on RISC-V ISA for AI acceleration and hardware design.
Run billion-parameter LLMs on embedded devices with extreme quantization for edge inference
re2c is a lexer generator that produces fast and flexible lexers for C, C++, D, Go, and other languages.
A Vue.js component library for building large-screen adaptive applications with support for ECharts visualizations.
A random instruction generator for RISC-V processor verification, written in Python.
A Rust library that provides a RISC-V Supervisor Binary Interface (SBI) for embedded Rust development.
RVVM is a RISC-V emulator written in C, allowing developers to run RISC-V applications on their systems.
A RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform, written in SystemVerilog.
A 32-bit superscalar RISC-V CPU implementation written in Verilog for FPGA and ASIC applications.
RISC-V tools including an ISA simulator and test suite for RISC-V processors.
A C++ plugin that transforms Grand Theft Auto V into a self-driving car research environment
A RISC-V out-of-order superscalar processor, not a developer discovery platform for vibe coders.
This is a repository for SiFive's Freedom platforms, which are open-source RISC-V development boards.
This repository contains a set of RISC-V tests used for verifying RISC-V processor implementations.
This is a course on building a RISC-V operating system from scratch, not a vibe coder tool.
This is a mod for Grand Theft Auto V that enables VR support, not a developer platform for vibe coders.
A template for simple System V init scripts, useful for managing system services on Linux.
A working draft of the proposed RISC-V V vector extension for low-power embedded systems.
A low-level library for accessing RISC-V processors in Rust, suitable for embedded systems development.
RISC-V XV6/Linux SoC, a low-power, open-source CPU design for developers working on hardware and embedded systems.
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