YosysHQ/yosys
Yosys is an open-source synthesis suite for register-transfer level (RTL) designs in VHDL, Verilog, and SystemVerilog.
C++
Backend & APIs
API Frameworks
ISC
4.3K
Stars
1.0K
Forks
Jan 5, 2013
Created
Mar 5, 2026
Last Updated
Project Analytics
Stars Growth (1 Month)
+46
+1.1% change
Avg Daily Growth (1 Month)
+1.6
stars per day
Fork/Star Ratio (All Time)
24.3%
High engagement
Lifetime Growth
0.9
stars/day over 4.8K days
Stars Over Time
Forks Over Time
Open Issues Over Time
Pull Requests Over Time
Commits Over Time
AI-Generated Tags
rtl-design
hdl
verilog
vhdl
open-source
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