Showing 21-28 of 28 projects
A package manager and build abstraction tool for FPGA/ASIC development, supporting Verilog, VHDL, and more.
A Python library for easy data augmentation of Chinese text corpora using the EDA (Easy Data Augmentation) technique.
A Python library that allows designing electronic circuits using Python code.
Horizon is a free, open-source EDA package for electronic hardware design and development.
Open-source CAD flow for FPGA research, enabling Verilog-to-routing design and verification
Modular hardware build system for ASIC, FPGA, and RTL development using Python, Verilog, and VHDL.
KLayout is a powerful open-source EDA (Electronic Design Automation) tool for working with GDSII and other layout formats.
An all-in-one VSCode plugin for HDL development, focusing on VHDL.
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