verilog-to-routing/vtr-verilog-to-routing
Open-source CAD flow for FPGA research, enabling Verilog-to-routing design and verification
C++
Developer Tools
Build Tools
NOASSERTION
1.2K
Stars
438
Forks
Jun 26, 2015
Created
Mar 5, 2026
Last Updated
Project Analytics
Stars Growth (1 Month)
+15
+1.3% change
Avg Daily Growth (1 Month)
+0.5
stars per day
Fork/Star Ratio (All Time)
36.2%
High engagement
Lifetime Growth
0.3
stars/day over 3.9K days
Stars Over Time
Forks Over Time
Open Issues Over Time
Pull Requests Over Time
Commits Over Time
AI-Generated Tags
fpga
verilog
eda
cad
placement
routing
synthesis
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