Explore Projects
Discover 39 open source projects
Showing 1-20 of 39 projects
adam-maj/tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
logisim-evolution/logisim-evolution
A digital logic design tool and simulator for educational and professional use.
LeiWang1999/FPGA
This GitHub repository provides tutorials and resources for developers interested in FPGA programming and development.
open-sdr/openwifi
Open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software for vibe coders.
YosysHQ/yosys
Yosys is an open-source synthesis suite for register-transfer level (RTL) designs in VHDL, Verilog, and SystemVerilog.
SpinalHDL/VexRiscv
A 32-bit RISC-V CPU implementation optimized for FPGA development and integration into SoC designs.
alexforencich/verilog-ethernet
Verilog components and modules for Ethernet networking on FPGA platforms
darklife/darkriscv
An open-source RISC-V CPU core implemented in Verilog, useful for hardware developers and FPGA enthusiasts.
The-OpenROAD-Project/OpenROAD
OpenROAD is an open-source, unified application that implements an RTL-to-GDS flow for circuit design and analysis.
jbush001/NyuziProcessor
A GPGPU microprocessor architecture designed for hardware acceleration of graphics and parallel computing.
stnolting/neorv32
An open-source RISC-V soft-core CPU and MCU-like SoC written in VHDL for embedded and hardware development.
alexforencich/verilog-axi
A Verilog library for implementing AXI components in FPGA projects.
pConst/basic_verilog
A collection of essential Verilog/SystemVerilog modules for FPGA and ASIC development, including UART, SPI, and other common peripherals.
SpinalHDL/SpinalHDL
SpinalHDL is a Scala-based hardware description language for FPGA and RTL development.
vortexgpgpu/vortex
This is a Verilog-based GPGPU hardware project for accelerating AI/ML workloads.
FPGAwars/icestudio
A visual editor for open FPGA boards, enabling developers to create and program FPGA designs with a drag-and-drop interface.
analogdevicesinc/hdl
A collection of HDL libraries and projects for FPGA and analog devices development
olofk/serv
SERV is a RISC-V CPU implementation targeting FPGA and ASIC platforms, built using Verilog.
riscv-mcu/e203_hbirdv2
An ultra-low power RISC-V core designed for embedded systems and IoT applications.
The-OpenROAD-Project/OpenLane
An automated RTL to GDSII flow for ASIC design and optimization based on OpenROAD, Yosys, Magic, and more.
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