Explore Projects
Discover 72 open source projects
Showing 41-60 of 72 projects
simdutf/simdutf
High-performance Unicode and Base64 routines used in Node.js, WebKit, Chromium, and more.
ultraembedded/riscv
Open-source RISC-V CPU Core (RV32IM) for ASIC and FPGA development
riscv-non-isa/riscv-asm-manual
RISC-V Assembly Programmer's Manual, a reference for developers working with RISC-V architecture.
succinctlabs/sp1
A zero-knowledge VM for verifying RISC-V program execution, focused on blockchain and Ethereum applications.
TheThirdOne/rars
RARS is a RISC-V assembler and runtime simulator for educational and development purposes.
riscv/learn
This repository tracks RISC-V education, training, courses, and other learning resources.
liangkangnan/tinyriscv
A simple and easy-to-understand RISC-V core implementation written in C.
riscv-software-src/opensbi
An open-source RISC-V supervisor binary interface, not focused on AI coding tools.
XUANTIE-RV/openc910
OpenXuantie - OpenC910 Core is a Verilog-based hardware design for the RISC-V C910 core, targeted at AI and ML workloads.
cnlohr/ch32fun
Open source minimal stack for the ch32 and ch5xx WCH RISC-V Microcontrollers
rcore-os/rCore-Tutorial-Book-v3
A tutorial book on how to write OS kernels in Rust, targeting the RISC-V architecture.
sysprog21/shecc
A self-hosting and educational C optimizing compiler, useful for building low-level system programming tools.
chili-chips-ba/wireguard-fpga
A hardware implementation of the WireGuard VPN protocol using a low-cost Artix7 FPGA with an open-source toolchain.
djiangtw/data-structures-in-practice-public
A hardware-aware guide to data structures for system software engineers.
hughperkins/VeriGPU
Open-source GPU in Verilog, loosely based on RISC-V ISA for AI acceleration and hardware design.
RightNow-AI/picolm
Run billion-parameter LLMs on embedded devices with extreme quantization for edge inference
chipsalliance/riscv-dv
A random instruction generator for RISC-V processor verification, written in Python.
rustsbi/rustsbi
A Rust library that provides a RISC-V Supervisor Binary Interface (SBI) for embedded Rust development.
LekKit/RVVM
RVVM is a RISC-V emulator written in C, allowing developers to run RISC-V applications on their systems.
openhwgroup/cv32e40p
A RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform, written in SystemVerilog.
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