ultraembedded/riscv

Open-source RISC-V CPU Core (RV32IM) for ASIC and FPGA development

Verilog
AI Coding Tools
BSD-3-Clause

1.7K

Stars

276

Forks

Aug 31, 2014

Created

Sep 18, 2021

Last Updated

Project Analytics

Stars Growth (1 Month)

+23

+1.4% change

Avg Daily Growth (1 Month)

+0.8

stars per day

Fork/Star Ratio (All Time)

16.7%

Good engagement

Lifetime Growth

0.4

stars/day over 4.2K days

Stars Over Time

Forks Over Time

Open Issues Over Time

Pull Requests Over Time

Commits Over Time

AI-Generated Tags

RISC-V
CPU Core
ASIC
FPGA
Verification

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