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ultraembedded/riscv

Open-source RISC-V CPU Core (RV32IM) for ASIC and FPGA development

1.7K
Archived
Verilog
#RISC-V#CPU Core#ASIC

chili-chips-ba/wireguard-fpga

A hardware implementation of the WireGuard VPN protocol using a low-cost Artix7 FPGA with an open-source toolchain.

1.3K
Active
Verilog
Embedded
Privacy Tools
#fpga#vpn#wireguard

ultraembedded/biriscv

A 32-bit superscalar RISC-V CPU implementation written in Verilog for FPGA and ASIC applications.

1.2K
Archived
Verilog
Embedded
API Frameworks
#risc-v#cpu#fpga

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