Showing 1-16 of 16 projects
An open-source process design kit for the SkyWater 130nm node, useful for ASIC and EDA development.
A highly configurable RISC-V core suitable for application and embedded development, with Linux support.
An open-source RISC-V soft-core CPU and MCU-like SoC written in VHDL for embedded and hardware development.
A collection of essential Verilog/SystemVerilog modules for FPGA and ASIC development, including UART, SPI, and other common peripherals.
SERV is a RISC-V CPU implementation targeting FPGA and ASIC platforms, built using Verilog.
An automated RTL to GDSII flow for ASIC design and optimization based on OpenROAD, Yosys, Magic, and more.
Open-source RISC-V CPU Core (RV32IM) for ASIC and FPGA development
A Haskell to VHDL/Verilog/SystemVerilog compiler for ASIC and FPGA development.
AXI SystemVerilog IP modules and verification infrastructure for high-performance on-chip communication.
A Verilog library for ASIC and FPGA designers, not focused on AI coding tools.
Open-source ASIC Bitcoin miner hardware project focused on mining efficiency and performance.
Open-source GPU in Verilog, loosely based on RISC-V ISA for AI acceleration and hardware design.
A Scala-based hardware accelerator for deep neural networks, part of Berkeley's AI hardware research.
A 32-bit superscalar RISC-V CPU implementation written in Verilog for FPGA and ASIC applications.
Modular hardware build system for ASIC, FPGA, and RTL development using Python, Verilog, and VHDL.
RISC-V XV6/Linux SoC, a low-power, open-source CPU design for developers working on hardware and embedded systems.
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