pulp-platform/axi
AXI SystemVerilog IP modules and verification infrastructure for high-performance on-chip communication.
SystemVerilog
Hardware
IP
NOASSERTION
1.5K
Stars
344
Forks
Apr 12, 2018
Created
Feb 25, 2026
Last Updated
Project Analytics
Stars Growth (1 Month)
+23
+1.5% change
Avg Daily Growth (1 Month)
+0.8
stars per day
Fork/Star Ratio (All Time)
22.8%
High engagement
Lifetime Growth
0.5
stars/day over 2.9K days
Stars Over Time
Forks Over Time
Open Issues Over Time
Pull Requests Over Time
Commits Over Time
AI-Generated Tags
asic
axi
axi4
axi4-lite
fpga
network-on-chip
rtl
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