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Discover 9 open source projects
Showing 1-9 of 9 projects
YosysHQ/yosys
Yosys is an open-source synthesis suite for register-transfer level (RTL) designs in VHDL, Verilog, and SystemVerilog.
openhwgroup/cva6
A highly configurable RISC-V core suitable for application and embedded development, with Linux support.
pConst/basic_verilog
A collection of essential Verilog/SystemVerilog modules for FPGA and ASIC development, including UART, SPI, and other common peripherals.
chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server.
clash-lang/clash-compiler
A Haskell to VHDL/Verilog/SystemVerilog compiler for ASIC and FPGA development.
pulp-platform/axi
AXI SystemVerilog IP modules and verification infrastructure for high-performance on-chip communication.
hdl-util/hdmi
A VHDL library for sending video/audio over HDMI on an FPGA platform.
openhwgroup/cv32e40p
A RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform, written in SystemVerilog.
splinedrive/kianRiscV
RISC-V XV6/Linux SoC, a low-power, open-source CPU design for developers working on hardware and embedded systems.
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