Showing 41-60 of 126 projects
A learning repository for FPGA, yosys, nextpnr, and RISC-V development.
A graphical processor simulator and assembly editor for the RISC-V ISA, useful for computer architecture education.
A 32-bit RISC-V CPU implementation optimized for FPGA development and integration into SoC designs.
C++ implementation of large language models ChatGLM-6B, ChatGLM2-6B, ChatGLM3 and GLM4(V) for natural language processing.
Deprecated network stress tool written in C# for developers who want to test server load and resilience.
A Chrome extension for quickly debugging front-end JavaScript code.
Political activism documentation on Chinese government censorship, human rights, and censorship circumvention techniques.
A modern, advanced, and portable bootloader and boot manager for various architectures and systems.
A highly configurable RISC-V core suitable for application and embedded development, with Linux support.
A C++ library providing wrappers for SIMD intrinsics and optimized mathematical functions.
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
Reko is a binary decompiler that allows developers to reverse-engineer and analyze compiled code.
A cross-platform UI library written in V for building modern, responsive user interfaces.
An open-source RISC-V CPU core implemented in Verilog, useful for hardware developers and FPGA enthusiasts.
An educational software system for learning about compilers, emulators, and hypervisors using RISC-V.
gem5 is an open-source computer system architecture simulator supporting various CPU architectures.
Dependency-free C compiler in Rust for various platforms
This GitHub repository appears to be related to a labor dispute lawsuit between Heshijun and 360, and does not appear to be a developer tool or platform.
A library for reflecting on and disassembling SPIR-V into high-level programming languages.
Generates a talking head video under the control of a reference image, audio, and V-Kps images.
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