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A Python library for solving linear programming and mixed integer programming problems.

2.4K

Stable

Python

API Frameworks

CLI Tools

Python

#constraints#mip#pulp

AXI SystemVerilog IP modules and verification infrastructure for high-performance on-chip communication.

1.5K

Active

SystemVerilog

CLI Tools

#asic#axi#axi4

A RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform, written in SystemVerilog.

1.2K

Experimental

SystemVerilog

Arduino & Embedded

#riscv#risc-v#cpu

An open-source microcontroller system based on the RISC-V architecture, suitable for embedded systems development.

1.0K

Archived

Arduino & Embedded

#microcontroller#risc-v#embedded-systems

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