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YosysHQ/yosys

Yosys is an open-source synthesis suite for register-transfer level (RTL) designs in VHDL, Verilog, and SystemVerilog.

4.3K
Active
C++
API Frameworks
CLI Tools
None
#rtl-design#hdl#verilog

BrunoLevy/learn-fpga

A learning repository for FPGA, yosys, nextpnr, and RISC-V development.

3.4K
Stable
C++
Arduino & Embedded
Tutorials & Courses
#fpga#risc-v#embedded

The-OpenROAD-Project/OpenLane

An automated RTL to GDSII flow for ASIC design and optimization based on OpenROAD, Yosys, Magic, and more.

1.7K
Stable
Python
API Frameworks
Databases
#asic#rtl2gds#vlsi

cariboulabs/cariboulite

CaribouLite is an open-source software-defined radio (SDR) project that turns a Raspberry Pi into a 6GHz transceiver.

1.3K
Experimental
C
Raspberry Pi
Radio
#sdr#radio#raspberry-pi

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