Explore Projects
Discover 72 open source projects
Showing 21-40 of 72 projects
BrunoLevy/learn-fpga
A learning repository for FPGA, yosys, nextpnr, and RISC-V development.
mortbopet/Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA, useful for computer architecture education.
SpinalHDL/VexRiscv
A 32-bit RISC-V CPU implementation optimized for FPGA development and integration into SoC designs.
limine-bootloader/limine
A modern, advanced, and portable bootloader and boot manager for various architectures and systems.
openhwgroup/cva6
A highly configurable RISC-V core suitable for application and embedded development, with Linux support.
xtensor-stack/xsimd
A C++ library providing wrappers for SIMD intrinsics and optimized mathematical functions.
probe-rs/probe-rs
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
uxmal/reko
Reko is a binary decompiler that allows developers to reverse-engineer and analyze compiled code.
darklife/darkriscv
An open-source RISC-V CPU core implemented in Verilog, useful for hardware developers and FPGA enthusiasts.
cksystemsteaching/selfie
An educational software system for learning about compilers, emulators, and hypervisors using RISC-V.
gem5/gem5
gem5 is an open-source computer system architecture simulator supporting various CPU architectures.
anthropics/claudes-c-compiler
Dependency-free C compiler in Rust for various platforms
stnolting/neorv32
An open-source RISC-V soft-core CPU and MCU-like SoC written in VHDL for embedded and hardware development.
rcore-os/rCore-Tutorial-v3
This is a tutorial for building a RISC-V operating system from scratch using the Rust programming language.
larsbrinkhoff/awesome-cpus
A comprehensive collection of CPU and MCU documentation for various architectures and platforms.
kfrlib/kfr
A fast, modern C++ DSP framework with features like FFT, Sample Rate Conversion, and Filters for audio processing.
lowRISC/ibex
Ibex is a small 32-bit RISC-V CPU core, previously known as zero-riscy, for hardware and system-level development.
olofk/serv
SERV is a RISC-V CPU implementation targeting FPGA and ASIC platforms, built using Verilog.
riscv-mcu/e203_hbirdv2
An ultra-low power RISC-V core designed for embedded systems and IoT applications.
sipeed/MaixPy-v1
MicroPython for K210 RISC-V, enabling easier edge AI development on low-power devices.
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