Showing 21-39 of 39 projects
Open-source RISC-V CPU Core (RV32IM) for ASIC and FPGA development
A Haskell to VHDL/Verilog/SystemVerilog compiler for ASIC and FPGA development.
Verilog PCI Express components for building high-performance hardware applications.
A Verilog synthesis flow for building Minecraft redstone circuits, targeting vibe coders.
Accelerates hardware synthesis with a high-level synthesis compiler
A Verilog library for ASIC and FPGA designers, not focused on AI coding tools.
OpenXuantie - OpenC910 Core is a Verilog-based hardware design for the RISC-V C910 core, targeted at AI and ML workloads.
A package manager and build abstraction tool for FPGA/ASIC development, supporting Verilog, VHDL, and more.
An IDE for IoT development with debugging, embedded, and hardware tooling for vibe coders.
A hardware implementation of the WireGuard VPN protocol using a low-cost Artix7 FPGA with an open-source toolchain.
Open-source GPU in Verilog, loosely based on RISC-V ISA for AI acceleration and hardware design.
Open-source CAD flow for FPGA research, enabling Verilog-to-routing design and verification
A 32-bit superscalar RISC-V CPU implementation written in Verilog for FPGA and ASIC applications.
A repository of gate-level simulators and tools for the original Game Boy, not related to AI coding tools.
Modular hardware build system for ASIC, FPGA, and RTL development using Python, Verilog, and VHDL.
A curated list of Hardware Description Languages (HDLs) like Verilog and VHDL for hardware development.
This is a hardware project for building a USB-C industrial camera using FPGA, MIPI CSI, and USB3 protocols.
RISC-V XV6/Linux SoC, a low-power, open-source CPU design for developers working on hardware and embedded systems.
An open-source Amiga 2/3/4000 graphics card written in Verilog for retro computing enthusiasts.
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