Explore Projects
Discover 12 open source projects
Showing 1-12 of 12 projects
logisim-evolution/logisim-evolution
A digital logic design tool and simulator for educational and professional use.
YosysHQ/yosys
Yosys is an open-source synthesis suite for register-transfer level (RTL) designs in VHDL, Verilog, and SystemVerilog.
SpinalHDL/VexRiscv
A 32-bit RISC-V CPU implementation optimized for FPGA development and integration into SoC designs.
ghdl/ghdl
GHDL is a VHDL 2008/93/87 simulator that can be used for hardware development and testing.
stnolting/neorv32
An open-source RISC-V soft-core CPU and MCU-like SoC written in VHDL for embedded and hardware development.
SpinalHDL/SpinalHDL
SpinalHDL is a Scala-based hardware description language for FPGA and RTL development.
clash-lang/clash-compiler
A Haskell to VHDL/Verilog/SystemVerilog compiler for ASIC and FPGA development.
olofk/fusesoc
A package manager and build abstraction tool for FPGA/ASIC development, supporting Verilog, VHDL, and more.
hdl-util/hdmi
A VHDL library for sending video/audio over HDMI on an FPGA platform.
siliconcompiler/siliconcompiler
Modular hardware build system for ASIC, FPGA, and RTL development using Python, Verilog, and VHDL.
drom/awesome-hdl
A curated list of Hardware Description Languages (HDLs) like Verilog and VHDL for hardware development.
Digital-EDA/Digital-IDE
An all-in-one VSCode plugin for HDL development, focusing on VHDL.
Stay in the loop
Get weekly updates on trending AI coding tools and projects.